Michael Frank of Sandia asked me for a slide based on material at WOLTE 2022 and documented in detail in technical report ZF10. Mike presented the slide below, followed by the PowerPoint notes text. Mike asked me to put the slide online so it could be referenced:
Upper left: Reversible transistor circuits, such as 2LAL or Q2LAL, in a cryostat would naturally have their power supply located at room temperature. In CMOS, all the energy flowing into the cryostat is turned into heat, but with reversible circuits most of the energy would flow back into the power supply. Energy would leave the cryostat with minimal losses instead of adding the 250x – 1000x overhead of a cryocooler. This means a cryogenic reversible transistor system created without needing resonators or an energy recycling power supply (hence actionable now). This method cannot exceed the cryocooler’s overhead factor, which would limit it to around 100x for 4 K operation.
Lower left: The lower left diagram is similar to one in the arXiv paper cited. Superconducting/transmon qubits have measurement times of around 1 μs, which implies the control system cannot be asked to make a decision in less than that time. A state machine with a ~1 MHz clock would be adequate. A slower clock would require complex architectural tricks similar to branch prediction. A faster clock would require less energy efficient classical electronics and would not increase the quantum computer’s throughput (because the throughput is determined by the qubits and all the classical electronics need to do is keep up). 1 MHz operation is well over 100x slower than room temperature CMOS and 4 K is often suggested for control electronics, so this and the previous two paragraphs suggest the method is actionable today.
Upper right: So, the baseline reversible logic controller would be a state machine whose function is to output tones – illustrated as a flow chart with musical measures as the boxes. Decisions would come from a room temperature decoder for error correction syndromes. The citation shows how to convert an error correction algorithm into a reversible circuit by substituting reversible circuit schematics into the flow chart – repurposing the lines of the flowchart as wires. Zettaflops, LLC has a layout of the test architecture shown. The circuits has not been fabbed; that is the next step.
Lower right: Zettaflops, LLC has a prototype layout for efabless ChipIgnite. The layout has not been fabbed yet. Some portion of the IP is expected to be made available as open source. Interested parties are encouraged to contact Zettaflops, LLC.
Erik DeBenedictis and Elie Track presented at the IEEE International Conference on Rebooting Computing (ICRC 2022) 8-9 December 2022 in San Francisco, CA, USA and Virtual.
The paper has been published as: DeBenedictis, Erik P., and Elie K. Track. “Rebooting Quantum Computing.” 2022 IEEE International Conference on Rebooting Computing (ICRC). IEEE, 2022. DOI: 10.1109/ICRC57508.2022.00010.
Feynman, Richard P. “Simulating physics with computers.” International Journal of theoretical physics 21.6/7 (1982).
Fredkin, Edward, and Tommaso Toffoli. “Conservative logic.” International Journal of theoretical physics 21.3-4 (1982): 219-253.
Younis, Saed G. Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic. Diss. Massachusetts Institute of Technology, 1994. https://dspace.mit.edu/handle/1721.1/7058.
Pauka, S. J., et al. “A cryogenic CMOS chip for generating control signals for multiple qubits.” Nature Electronics 4.1 (2021): 64-70. DOI: https://doi.org/10.1038/s41928-020-00528-y.
Sirois, Adam J., et al. “Josephson microwave sources applied to quantum information systems.” IEEE Transactions on Quantum Engineering 1 (2020): 1-7. DOI: https://doi.org/10.1109/TQE.2020.3045682.
Erik DeBenedictis attended the Quantum Resource Estimation conference on June 18, 2022. This page has is the slide decks that were presented and two additional documents.
The zip files below comprise the AA (Adiabatic Analysis) ngspice software. The software is licensed under Apache 2.0. There is no repository for changes at this time.
Version of 3:05 PM 3/13/2022
This release comprises eight .cir files. Installation instructions are in comments towards the end of aa.cir.
Supports multiple devices:
(MD=2) Compatibility check with e.cir, which uses the built-in BSIM3 model with default parameters.
(MD=3) Built-in BSIM3 model with default parameters.
(MD=4) BSIM4 test modelcards from the ngspice distribution. You must manually move the modelcard files; see comments in aa.cir.
(MD=5) Sky130. You must install the Sky130 PDK and “uncomment” some lines.
(MD=6) [undisclosed SOI]. Not for general use at this time.
Supports the following circuits:
Q2LAL shift registers
S2LAL shift registers
Two versions of a quantum computer controller based on Q2LAL
A CMOS work alike for one of the quantum computer controllers
Learning about the code and regression testing:
Running aa.cir with no modifications will produce the same output as running e.cir. This is a regression test.
The top of aa.cir contains a series of control lines of similar format. For purposes of identification, they start with *.param or .param. All but one of these lines should be commented out, meaning the one that is not commented out will control the run.
Each run will produce some plots and append a summary line to Adia.csv and CMOS.csv. (The current version of this software also appends a second line with the simulation run time.) You can open .csv files with Excel.
Summary lines have been incorporated into aa.cir immediately following the .param line that controlled run, forming another type of regression test. The summary lines include the energy dissipated during initialization and the remainder of the simulation run. If your run’s dissipation is the same (to five decimal places) as the one incorporated in aa.cir, the software is probably running correctly.
The summary lines in aa.cir have been manually edited so the last field contains the time and date of the run, the run time in seconds, and the name of the computer in the developer’s office that executed the run.
The scripts in this software are intended to be changed by the user. Some friendly advice is to run regression tests frequently and keep a lot of backup files because ngspice scripts are hard to debug.
The following zip file contains password-protected files for the convenience of the developer. You should not need these files because they are available on the Internet.
Erik P. DeBenedictis Accepted manuscript for publication in IEEE Computer July 17, 2020; updated August 21, 2020
Quantum computers are available via the Internet for students and small-scale research. What if similar access could be extended to quantum hardware?
I took a class on integrated circuit design when I was a student in 1981. The class project was for each student to design and test a CMOS circuit. I designed a CMOS arbiter, a circuit used to reliably detect which of two input signals arrives first. The chip was fabricated as part of a multiproject wafer during the first run of ARPA’s (now DARPA’s) MOS Implementation Service (MOSIS) and delivered to me as a chip bonded into a package—like a simplified version of the one shown in Figure 1—and I tested it with an oscilloscope.
Fig. 1. A hybrid classical-quantum module.1 The small square indicated contains two qubits and the larger square below it contains single flux quantum (SFQ) logic. The test fixture carries both DC and microwave signals.
However, the version shown in Figure 1 is a quantum module built by a professional research team1 out of components created by governmental and commercial fabricators (fabs) that could become the quantum equivalent of my 1981 CMOS chip. The central gray box in Figure 1 contains qubits bonded on top of a somewhat larger classical electronics chip. Unlike my 1981 chip, some of the leads in Figure 1 carry microwave signals, and the module operates at millikelvins. Although the module in Figure 1 is not a complete quantum computer, its structure and the process of creating it would give students hands-on experience or support experimental research projects within the bounds of the module’s external interfaces.
Quantum technology is roughly as mature as CMOS was in 1981, making it feasible to offer students and small research groups access to quantum hardware prototyping. This concept has been discussed in an IEEE Quantum Initiative working group, and I’m writing about it here as a noncommercial concept that IEEE Members could champion in the public interest.
A brief history of integrated circuits
Integrated circuits were originally designed by cutting plastic such as Rubylith and handcrafting what were essentially photographic negatives. The method’s scale-up limitations are obvious. At some point, companies started writing their own computer-aided design (CAD) software, which codified design rules such as the minimum dimensions of wires or transistors and the various spacings between them. The design processes were proprietary because they gave the electronics manufacturer that sold the chips a competitive advantage in speed, density, and reliability. Proprietary design processes preserved this competitive advantage but meant that the employees had to be trained on the job.
To make the semiconductor industry scalable, universities championed relaxed “least common denominator” design rules that were independent of any specific process.2 Process-independent design rules would work on proprietary fab lines, thus foreshadowing the emergence of a separate CAD industry, semiconductor foundries, and a systematic way to train the workforce that has engineered all of the chips in use today.
ARPA’s MOSIS made chip design widely accessible. The main idea was that students from many universities would create chip designs using generic design rules as class projects or for theses. Student designs are typically so small that the overhead of commercial contracting is burdensome; therefore, many student designs could be combined into a single fab run. The MOSIS operational model is one in which the layout from multiple student projects would be combined by the MOSIS operator into a single set of masks and then manufactured by any foundry that could support the generic design rules.
MOSIS is in operation today (https://mosis.com). MOSIS is the main chip fabrication option available to students, but it is also a practical option for startups and, in fact, any researcher that wants create a handful of small chips to test a hardware idea.
“Quantum Access”
Quantum computer systems are now accessible via the Internet for quantum software training and small-scale research. Extending access to quantum hardware could follow and then extend the semiconductor MOSIS paradigm. The IEEE Quantum Initiative is using the name quantum access for a potential nonprofit service that
fabricates quantum components like those shown in Figure 1, using unique quantum features such as cryogenic packaging, microwave signals, qubits, and control electronics, extending the suite of available features over time as discussed later in this article.
at the operational level, the operator would contract with fabs, design tool suppliers, and companies that can perform certain assembly activities, essentially aggregating funds from small users to create a fab run that is compatible with standard industrial processes.
organizes, but does not create, educational materials, process design kits (PDKs), and generic intellectual property (IP) that enables users to get up to speed quickly.
The quantum access user would be a student, researcher, or start-up company that wants to try out a hardware idea in quantum information technology. Student interest would start by taking classes, perhaps those specifically developed for quantum access. All users would then require access to a capital-intensive fab and help construct a “test harness,” that is, a simple system, to test an idea. Table 1 summarizes the different user classes.
To try out the idea quickly and at low cost, quantum access would also curate information about the design of standard components, called IP, which users could include with no modification and hence with less effort or risk of error. For example, a user with an idea for a new microwave amplifier could prototype his innovative amplifier circuit but use open source, tested designs for filters, drivers, and so on.
Quantum access would also be a source of reliable information about physical test apparatus (including cryogenic). This would enable the user (or the user’s university or employer) to place an order for commercially available equipment and have some assurance that the purchased parts would work together and also work with the custom parts created by quantum access’s foundries. Unlike the situation I experienced in 1981, it may be possible for a cryogenic test system to be constructed on a centralized location and accessed via the Internet. Quantum access should anticipate that a few projects will become unusually successful and provide a path to volume manufacturing. Thus, start-ups, the government, and government labs would have a role that eventually outgrows the quantum access model; these are listed near the bottom of Table 1.
Segment
Objectives
Typical interaction
Technology and IP
Students
Hands on experience to augment classwork
University uses educational materials that highlight use of quantum access; submits simple components from class projects for fabrication
Educational modules where indicated; a standard PDK and generic IP from others; little interest in commercializing IP they created
University research
Foundry for trying out novel ideas for a thesis or faculty research projects
Fab using standard processes with new designs; researcher may go on site
May modify PDK or create a new one; interest in IP for publication or commercialization through university licensing
Commercial users
Prototyping hardware concepts, R&D missions, and derivative technology
Fab using standard processes with new designs; employees may go on site.
May modify the PDK; design may be commercially sensitive and must be kept from other user; new IP will be owned by the user.
Government agencies
Prototyping non-standard technology
Requests from government research programs; researchers may go on site, as well as government program administrators
Standard or government supplied PDKs; the latter could be released commercially over time. Government IP may be sensitive
Government research labs
Exploring high-risk or niche technology that may not be destined for commercialization
Fab request directly from government entity.
Standard or government supplied PDKs; government may create a fab; government IP may be sensitive, but may not be intended for commercialization
Original table courtesy of Synopsys; modified by author
Table 1: Quantum Access user classes
Quantum Access maturation process
It didn’t occur to me in 1981 to ask which semiconductor process would be used for my CMOS MOSIS chip. I was simply glad there was one option instead of no options. Quantum access could start out similarly by supporting a single quantum-system type (for example, a qubit type) and expand the number of types over time. As an example of where this might go, the semiconductor MOSIS service currently supports 20 semiconductor processes from two foundries.
Qubits
Superconducting qubits (transmons) seem to have reached the maturity level necessary for quantum access to be viable. Transmons are physically large and do not require many mask layers, making current designs mature enough for general production. Although research on superconducting qubits continues, the quantum industry is growing and expected to specialize as it matures, so some students and new corporate or university entrants may want to avoid well-trodden areas, such as making their own qubits. Instead, they might use generic qubits for research projects in other areas under the assumption that their results would be combined with the latest qubits prior to production.
Even though specific plans are yet to be determined, ion traps may be the second qubit type offered. Experimental ion traps used for quantum computer-type applications are manufactured by government labs. Some of these labs fabricate for other parties, although foundry access will need to mature before ion traps will be viable in quantum access.
Classical control systems
Transmon systems are almost universally controlled by room-temperature lab equipment interfacing via electronics at various temperature stages. The electronics may be passive, transistor, or Josephson junction (JJ) based.
Just as I tested my CMOS chip in 1981 using an oscilloscope, the idea is that quantum access would engage with test equipment and cryogenic equipment manufacturers from the start. Although quantum technology is not ready for formal standards, researchers need information on signal flow through cryogenic stages and what to expect from test equipment. Test equipment and cryogenics will inevitably evolve; therefore, these manufacturers are expected to be interested in feedback from users.
As quantum technologies mature, there is the belief that room-temperature lab equipment will be supplemented by electronics close to the qubits for reasons of signal latency, bandwidth, and thermal backflow. Broadly speaking, the two leading options are cryo CMOS and superconducting electronics based on classical JJs.
For example, Intel and Microsoft fund quantum control electronics using existing CMOS processes of a modest linewidth (for example, 28 nm) and that are in commercial use for the Internet of Things and other timely business opportunities.3, 4 Many room-temperature semiconductor processes work at cryogenic temperatures, although some work better than others. It is expected that, over time, special cryo CMOS processes will be developed for quantum information, further differentiating quantum access from MOSIS. Lincoln Labs, SeeQC, Skywater, and others use JJ-based control circuitry,1, 5 which has different properties in terms of density, heat dissipation, and so forth.
Unlike the simple fab processes used by transmon qubits, classical control systems will have roughly the same process complexity (for example, the number of layers) as that of today’s CMOS, implying an expensive fab. JJ processes are destined to be equally complex but are still under development, including through government R&D funding. When it is time to support ion traps, quantum access would need to embrace a different fab process, electronics with different operating voltages, optical (laser) signaling, and optical components.
Design tools and IP
Integrated circuits have not been designed directly by humans for decades, but rather by electronic design automation (EDA) software that synthesizes circuits, translates them into physical layouts, and then simulates their performance. Thus, new quantum-relevant design principles will need to be embedded into design tools. It will be essential that industry fosters the development of quantum-specific design tools and disseminates to the quantum workforce the knowledge for how to use them.
The idea is that quantum access would work with EDA companies to ensure that students and other users have the most advanced and compatible tools available from industry to produce designs for quantum access. Quantum access would also serve as a repository for open access hardware designs, subject to limitations on the distribution of this information due to proprietary or government restrictions.
Educational materials
Although quantum access is not expected to distribute educational materials directly, it may end up with a central role in making educational materials effective. Future quantum engineering students will need to take classes on the design of qubits and various forms of control electronics. These classes would teach best practices and have a role in defining the terminology, circuits, and so forth that students bring to the workforce after they graduate. The developers of educational materials could coordinate with quantum access to ensure that students do homework assignments and class projects in ways that are not just generally correct but compatible with the specific methods and customs used in industry.
If experience with the semiconductor MOSIS activity decades ago recurs, quantum access could influence the development of an industrial quantum infrastructure and, possibly, standards in the quantum engineering domain.
It seems natural that the quantum industry will develop commercial infrastructure similar to the existing semiconductor industry, including fabs, fabless design houses, design tool vendors, and IP suppliers, all of which would be coordinated by standards. Yet, the industry can and should partner with noncommercial organizations, such as IEEE, the Quantum Economic Development Consortium, universities, and, we suggest here, a new quantum access entity.
Building a fab costs a lot of money, yet the quantum access concept does not involve building fabs. Instead, it organizes people to cooperate toward the common goal of educating students and supporting early-stage research, both of which are imperative and worthwhile goals. This article describes a worthwhile goal in the hope that readers will lend support.
Acknowledgements
Although references made to my 1981 MOSIS project are entirely my responsibility, quantum access is the topic in a semiformal IEEE Quantum Initiative working group. The ideas herein are due to approximately a dozen people in that group. Individuals from Raytheon, Baylor University, Syracuse University, the Massachusetts Institute of Technology, and Synopsys assisted with preparing this article.
References
R. Das et al., “Cryogenic qubit integration for quantum computing.” In Proc. 2018 IEEE 68th Electronic Components and Technology Conf. (ECTC), pp. 504-514. doi: 10.1109/ECTC.2018.00080.
C. Mead and L. Conway, Introduction to VLSI Systems, vol. 1080. Reading, MA: Addison-Wesley, 1980.
B. Patra et al., “A scalable Cryo-CMOS 2-to-20GHz digitally-intensive controller for 4× 32 frequency multiplexed spin qubits/transmons in 22nm FinFET technology for quantum computers,” in Proc. 2020 Int. Solid-State Circuits Conf., pp. 304-306. doi 10.1109/ ISSCC19947.2020.9063109.
S. J. Pauka et al., A cryogenic interface for controlling many qubits, 2019 [Online]. Available https:arXiv:1912.01299.
R. McDermott et al., “Quantum–classical interface based on single flux quantum digital logic,” Quantum Sci. Technol. vol 3, no. 2, p. 024004, 2018. doi: 10.1088/2058-9565/aaa3a0.
This brief technical note is in response to the recently introduced S2LAL reversible logic family, which is a static version of the 2LAL family. I created inversion for 2LAL in a previous report, and create inversion for S2LAL here using similar principles. S2LAL requires quad-rail logic because there is no other source of inversion. Quad-rail logic is not necessary with the inversion in this note, although it can still be used. The availability of inversion will result in much smaller circuits in some cases.
This report improves upon what was originally the T-Gate shift register and renamed to 2-Level Adiabatic Logic (2LAL) by Mike Frank when he enhanced it into a logic family. 2, 3 This report also offers improvements to the SCRL logic family. 2LAL and SCRL have been proposed as energy efficient alternatives to room-temperature CMOS, a goal that depends upon high throughput and high speed. However, this report applies to quantum computer control electronics where Josephson junctions are available for logic functions but transistor circuitry such as 2LAL and SCRL provide much higher density for memory and subfunctions requiring high complexity. Since high speed and high throughput are available from Josephson junctions, the transistorized logic has less need for these attributes. To better serve quantum computer control applications, this report includes improvements to the clocking structure to support inverting gates without doubling the number of logic rails and reducing density. The clocking improvements also make the design of data permutation logic more efficient. This is an important optimization because some common digital building blocks are just data permutations, such as busses, multiplexers, and addressing logic. This report also proposes a way to use Fully Depleted Silicon on Insulator (FDSOI) transistors to eliminate half the transistors from some stages.
