Zettaflops.org was mentioned at the Texas Symposium on Computing with Emerging Technologies (ComET), October 30, 2023.
Michael Frank of Sandia asked me for a slide based on material at WOLTE 2022 and documented in detail in technical report ZF10. Mike presented the slide below, followed by the PowerPoint notes text. Mike asked me to put the slide online so it could be referenced:
Upper left: Reversible transistor circuits, such as 2LAL or Q2LAL, in a cryostat would naturally have their power supply located at room temperature. In CMOS, all the energy flowing into the cryostat is turned into heat, but with reversible circuits most of the energy would flow back into the power supply. Energy would leave the cryostat with minimal losses instead of adding the 250x – 1000x overhead of a cryocooler. This means a cryogenic reversible transistor system created without needing resonators or an energy recycling power supply (hence actionable now). This method cannot exceed the cryocooler’s overhead factor, which would limit it to around 100x for 4 K operation.
Lower left: The lower left diagram is similar to one in the arXiv paper cited. Superconducting/transmon qubits have measurement times of around 1 μs, which implies the control system cannot be asked to make a decision in less than that time. A state machine with a ~1 MHz clock would be adequate. A slower clock would require complex architectural tricks similar to branch prediction. A faster clock would require less energy efficient classical electronics and would not increase the quantum computer’s throughput (because the throughput is determined by the qubits and all the classical electronics need to do is keep up). 1 MHz operation is well over 100x slower than room temperature CMOS and 4 K is often suggested for control electronics, so this and the previous two paragraphs suggest the method is actionable today.
Upper right: So, the baseline reversible logic controller would be a state machine whose function is to output tones – illustrated as a flow chart with musical measures as the boxes. Decisions would come from a room temperature decoder for error correction syndromes. The citation shows how to convert an error correction algorithm into a reversible circuit by substituting reversible circuit schematics into the flow chart – repurposing the lines of the flowchart as wires. Zettaflops, LLC has a layout of the test architecture shown. The circuits has not been fabbed; that is the next step.
Lower right: Zettaflops, LLC has a prototype layout for efabless ChipIgnite. The layout has not been fabbed yet. Some portion of the IP is expected to be made available as open source. Interested parties are encouraged to contact Zettaflops, LLC.
The following are additional references: