This report improves upon what was originally the T-Gate shift register and renamed to 2-Level Adiabatic Logic (2LAL) by Mike Frank when he enhanced it into a logic family. 2, 3 This report also offers improvements to the SCRL logic family.

2LAL and SCRL have been proposed as energy efficient alternatives to room-temperature CMOS, a goal that depends upon high throughput and high speed. However, this report applies to quantum computer control electronics where Josephson junctions are available for logic functions but transistor circuitry such as 2LAL and SCRL provide much higher density for memory and subfunctions requiring high complexity. Since high speed and high throughput are available from Josephson junctions, the transistorized logic has less need for these attributes.

To better serve quantum computer control applications, this report includes improvements to the clocking structure to support inverting gates without doubling the number of logic rails and reducing density.

The clocking improvements also make the design of data permutation logic more efficient. This is an important optimization because some common digital building blocks are just data permutations, such as

busses, multiplexers, and addressing logic.

This report also proposes a way to use Fully Depleted Silicon on Insulator (FDSOI) transistors to eliminate half the transistors from some stages.

v. 1.03 http://itrs.org/ar/CATC/2LAL_Inv_Q.pdf Alt. source /ar/CATC/2LAL_Inv_Q.pdf

v. 1.02 http://itrs.org/ar/CATC/2LAL_Inv_P5.pdf Alt. source /ar/CATC/2LAL_Inv_P5.pdf

v. 1.01 http://itrs.org/ar/CATC/2LAL_Inv_10.pdf Alt. source /ar/CATC/2LAL_Inv_10.pdf