Category: CATC

This document proposes an “unconventional computing” technology for controlling quantum computers, including specific application to quantum memory based on posits. While improved qubits are a top priority in quantum computing, existing approaches for classical control systems
limit scale up to 50-1,000 qubits due to wiring between the cryogenic environment and room temperature or excessive (CV2) dissipation in cryogenic electronics.

v 1.02 http://itrs.org/ar/CATC/CATC_posit_v26g.pdf Alt. source /ar/CATC/CATC_posit_v26g.pdf

v 1.01 http://itrs.org/ar/CATC/CATC_posit_v25.pdf Alt. source /ar/CATC/CATC_posit_v25.pdf

v 1 http://itrs.org/ar/CATC/CATC_posit_v22d.pdf Alt. source /ar/CATC/CATC_posit_v22d.pdf

To illustrate the concept of FET-only adiabatic permutation stages as described in ref. 1, these test circuits demonstrate both 2LAL and SCRL 4-bit barrel shifters implemented with FET-only permutation stages.
The circuits are in a test harness comprising a four- or five-stage shift register preloaded with data patterns 1, 2, 4, 8 and a shift count pattern of 3, 3, 3, 3 places. The files should be available wherever the reader obtained this document, but the main files have been pasted into the appendix of this document as a failsafe. The circuits are designed for ngspice version 30 and use the built-in BSIM 3.3.0 transistor model, with voltage sources to alter gate bias (which is not realistic)

http://itrs.org/ar/CATC/barrel.pdf Alt. source /ar/CATC/barrel.pdf

http://itrs.org/ar/CATC/ZF003_1.0_Barrel.zip Alt. source /ar/CATC/ZF003_1.0_Barrel.zip

Inspired by recent interest in quantum computing and recent studies of cryo CMOS for control electronics, this paper presents a hybrid semiconductor-superconductor approach for engineering scalable computing systems that operate across the gradient between room temperature and the temperature of a cryogenic payload. Such a hybrid computer architecture would have unique suitability to quantum computers, scalable sensors, and the quantum internet. The approach is enabled by Cryogenic Adiabatic Transistor Circuits (CATCs), a novel way of using adiabatic circuits to substantially reduce cooling requirements. In a hybrid chip of CATCs and a second technology, such as Josephson junctions (JJs) or cryo CMOS, the CATCs complement the speed, power, and density of the second technology as well as becoming a longsought cryogenic memory. This paper describes higher-level design principles for CATC hybrids with a quantum computer control system that includes CATC memory, an FPGA-like logic module that uses CATC for dense configuration logic and JJs for fast configured logic, and I/O subsystems including microwave modulators and low frequency control signals.

ArXiv article v. 1.05 https://arxiv.org/pdf/1912.11532

v. 1.03 http://itrs.org/ar/CATC/QCuHSS_53ver5.pdf Alt. source /ar/CATC/QCuHSS_53ver5.pdf

v. 1.02 http://itrs.org/ar/CATC/DPfC_52ver4.pdf Alt. source /ar/CATC/DPfC_52ver4.pdf

v. 1.01 http://itrs.org/ar/CATC/DPfC_51.pdf Alt. source /ar/CATC/DPfC_51.pdf

v. 1 http://itrs.org/ar/CATC/DPfC_50.pdf Alt. source /ar/CATC/DPfC_50.pdf