Author: Erik

This brief technical note is in response to the recently introduced S2LAL reversible logic family, which is a static version of the 2LAL family.
I created inversion for 2LAL in a previous report, and create inversion for S2LAL here using similar principles. S2LAL requires quad-rail logic because there is no other source of inversion. Quad-rail logic is not necessary with the inversion in this note, although it can still be used. The availability of inversion will result in much smaller circuits in some cases.

v. 1.01 http://itrs.org/ar/CATC/S2LAL_Inv_1.01.pdf Alt. source /ar/CATC/S2LAL_Inv_1.01.pdf

original version http://itrs.org/ar/CATC/S2LAL_Inv.pdf Alt. source /ar/CATC/S2LAL_Inv.pdf

This report improves upon what was originally the T-Gate shift register and renamed to 2-Level Adiabatic Logic (2LAL) by Mike Frank when he enhanced it into a logic family. 2, 3 This report also offers improvements to the SCRL logic family.
2LAL and SCRL have been proposed as energy efficient alternatives to room-temperature CMOS, a goal that depends upon high throughput and high speed. However, this report applies to quantum computer control electronics where Josephson junctions are available for logic functions but transistor circuitry such as 2LAL and SCRL provide much higher density for memory and subfunctions requiring high complexity. Since high speed and high throughput are available from Josephson junctions, the transistorized logic has less need for these attributes.
To better serve quantum computer control applications, this report includes improvements to the clocking structure to support inverting gates without doubling the number of logic rails and reducing density.
The clocking improvements also make the design of data permutation logic more efficient. This is an important optimization because some common digital building blocks are just data permutations, such as
busses, multiplexers, and addressing logic.
This report also proposes a way to use Fully Depleted Silicon on Insulator (FDSOI) transistors to eliminate half the transistors from some stages.

v. 1.03 http://itrs.org/ar/CATC/2LAL_Inv_Q.pdf Alt. source /ar/CATC/2LAL_Inv_Q.pdf

v. 1.02 http://itrs.org/ar/CATC/2LAL_Inv_P5.pdf Alt. source /ar/CATC/2LAL_Inv_P5.pdf

v. 1.01 http://itrs.org/ar/CATC/2LAL_Inv_10.pdf Alt. source /ar/CATC/2LAL_Inv_10.pdf

This document proposes an “unconventional computing” technology for controlling quantum computers, including specific application to quantum memory based on posits. While improved qubits are a top priority in quantum computing, existing approaches for classical control systems
limit scale up to 50-1,000 qubits due to wiring between the cryogenic environment and room temperature or excessive (CV2) dissipation in cryogenic electronics.

v 1.02 http://itrs.org/ar/CATC/CATC_posit_v26g.pdf Alt. source /ar/CATC/CATC_posit_v26g.pdf

v 1.01 http://itrs.org/ar/CATC/CATC_posit_v25.pdf Alt. source /ar/CATC/CATC_posit_v25.pdf

v 1 http://itrs.org/ar/CATC/CATC_posit_v22d.pdf Alt. source /ar/CATC/CATC_posit_v22d.pdf

To illustrate the concept of FET-only adiabatic permutation stages as described in ref. 1, these test circuits demonstrate both 2LAL and SCRL 4-bit barrel shifters implemented with FET-only permutation stages.
The circuits are in a test harness comprising a four- or five-stage shift register preloaded with data patterns 1, 2, 4, 8 and a shift count pattern of 3, 3, 3, 3 places. The files should be available wherever the reader obtained this document, but the main files have been pasted into the appendix of this document as a failsafe. The circuits are designed for ngspice version 30 and use the built-in BSIM 3.3.0 transistor model, with voltage sources to alter gate bias (which is not realistic)

http://itrs.org/ar/CATC/barrel.pdf Alt. source /ar/CATC/barrel.pdf

http://itrs.org/ar/CATC/ZF003_1.0_Barrel.zip Alt. source /ar/CATC/ZF003_1.0_Barrel.zip

Inspired by recent interest in quantum computing and recent studies of cryo CMOS for control electronics, this paper presents a hybrid semiconductor-superconductor approach for engineering scalable computing systems that operate across the gradient between room temperature and the temperature of a cryogenic payload. Such a hybrid computer architecture would have unique suitability to quantum computers, scalable sensors, and the quantum internet. The approach is enabled by Cryogenic Adiabatic Transistor Circuits (CATCs), a novel way of using adiabatic circuits to substantially reduce cooling requirements. In a hybrid chip of CATCs and a second technology, such as Josephson junctions (JJs) or cryo CMOS, the CATCs complement the speed, power, and density of the second technology as well as becoming a longsought cryogenic memory. This paper describes higher-level design principles for CATC hybrids with a quantum computer control system that includes CATC memory, an FPGA-like logic module that uses CATC for dense configuration logic and JJs for fast configured logic, and I/O subsystems including microwave modulators and low frequency control signals.

ArXiv article v. 1.05 https://arxiv.org/pdf/1912.11532

v. 1.03 http://itrs.org/ar/CATC/QCuHSS_53ver5.pdf Alt. source /ar/CATC/QCuHSS_53ver5.pdf

v. 1.02 http://itrs.org/ar/CATC/DPfC_52ver4.pdf Alt. source /ar/CATC/DPfC_52ver4.pdf

v. 1.01 http://itrs.org/ar/CATC/DPfC_51.pdf Alt. source /ar/CATC/DPfC_51.pdf

v. 1 http://itrs.org/ar/CATC/DPfC_50.pdf Alt. source /ar/CATC/DPfC_50.pdf