Enhancements to Adiabatic Logic for Quantum Computer Control Electronics

This report improves upon what was originally the T-Gate shift register and renamed to 2-Level Adiabatic Logic (2LAL) by Mike Frank when he enhanced it into a logic family. 2, 3 This report also offers improvements to the SCRL logic family.
2LAL and SCRL have been proposed as energy efficient alternatives to room-temperature CMOS, a goal that depends upon high throughput and high speed. However, this report applies to quantum computer control electronics where Josephson junctions are available for logic functions but transistor circuitry such as 2LAL and SCRL provide much higher density for memory and subfunctions requiring high complexity. Since high speed and high throughput are available from Josephson junctions, the transistorized logic has less need for these attributes.
To better serve quantum computer control applications, this report includes improvements to the clocking structure to support inverting gates without doubling the number of logic rails and reducing density.
The clocking improvements also make the design of data permutation logic more efficient. This is an important optimization because some common digital building blocks are just data permutations, such as
busses, multiplexers, and addressing logic.
This report also proposes a way to use Fully Depleted Silicon on Insulator (FDSOI) transistors to eliminate half the transistors from some stages.

v. 1.03 Alt. source /ar/CATC/2LAL_Inv_Q.pdf

v. 1.02 Alt. source /ar/CATC/2LAL_Inv_P5.pdf

v. 1.01 Alt. source /ar/CATC/2LAL_Inv_10.pdf


An Unconventional Computing Approach for Quantum Computer Control and Quantum Memory

This document proposes an “unconventional computing” technology for controlling quantum computers, including specific application to quantum memory based on posits. While improved qubits are a top priority in quantum computing, existing approaches for classical control systems
limit scale up to 50-1,000 qubits due to wiring between the cryogenic environment and room temperature or excessive (CV2) dissipation in cryogenic electronics.

v 1.02 Alt. source /ar/CATC/CATC_posit_v26g.pdf

v 1.01 Alt. source /ar/CATC/CATC_posit_v25.pdf

v 1 Alt. source /ar/CATC/CATC_posit_v22d.pdf


Barrel Shifter Permutation Circuit, 2LAL and SCRL

To illustrate the concept of FET-only adiabatic permutation stages as described in ref. 1, these test circuits demonstrate both 2LAL and SCRL 4-bit barrel shifters implemented with FET-only permutation stages.
The circuits are in a test harness comprising a four- or five-stage shift register preloaded with data patterns 1, 2, 4, 8 and a shift count pattern of 3, 3, 3, 3 places. The files should be available wherever the reader obtained this document, but the main files have been pasted into the appendix of this document as a failsafe. The circuits are designed for ngspice version 30 and use the built-in BSIM 3.3.0 transistor model, with voltage sources to alter gate bias (which is not realistic) Alt. source /ar/CATC/barrel.pdf Alt. source /ar/CATC/


Quantum Computer Control using Novel, Hybrid Semiconductor-Superconductor Electronics

Inspired by recent interest in quantum computing and recent studies of cryo CMOS for control electronics, this paper presents a hybrid semiconductor-superconductor approach for engineering scalable computing systems that operate across the gradient between room temperature and the temperature of a cryogenic payload. Such a hybrid computer architecture would have unique suitability to quantum computers, scalable sensors, and the quantum internet. The approach is enabled by Cryogenic Adiabatic Transistor Circuits (CATCs), a novel way of using adiabatic circuits to substantially reduce cooling requirements. In a hybrid chip of CATCs and a second technology, such as Josephson junctions (JJs) or cryo CMOS, the CATCs complement the speed, power, and density of the second technology as well as becoming a longsought cryogenic memory. This paper describes higher-level design principles for CATC hybrids with a quantum computer control system that includes CATC memory, an FPGA-like logic module that uses CATC for dense configuration logic and JJs for fast configured logic, and I/O subsystems including microwave modulators and low frequency control signals.

ArXiv article v. 1.05

v. 1.03 Alt. source /ar/CATC/QCuHSS_53ver5.pdf

v. 1.02 Alt. source /ar/CATC/DPfC_52ver4.pdf

v. 1.01 Alt. source /ar/CATC/DPfC_51.pdf

v. 1 Alt. source /ar/CATC/DPfC_50.pdf


Cryogenic Adiabatic Transistor Circuits Linc Labs

November 22, 2019

PDF slide deck Alt. source /ar/CATC/CATC_Linc_v6.pdf

PowerPoint slide deck Alt. source /ar/CATC/CATC_Linc_v6.pptx


A Memory Option for Quantum Computer Control: Cryogenic Adiabatic Transistor Circuits

Presentation at JJ workshop 2019.

PDF slide deck Alt. source /ar/CATC/JJ%20CATC%20v6.pdf

PowerPoint Alt. source /ar/CATC/JJ%20CATC%20v6.pptx


Cryogenic Adiabatic Transistor Circuits JJ Workshop

Presentation at JJ Workshop 2019

PDF slide deck Alt. source /ar/CATC/JJ%20CATC%20v6.pdf

Power Point slide deck Alt. source /ar/CATC/JJ%20CATC%20v6.pptx


Cryogenic Adiabatic Transistor Circuits

Original files are here /ar/CATC.

Space Computing

Fault-Tolerant Spaceborne Computing Employing New Technologies, 2018

This meeting was the beginning of the end of the era.

The 2018 meeting was collocated with MITRE in Massachusetts.

The 2019 meeting was collocated with SMC-IT in Pasadena.

The 2020 meeting was canceled due to COVID-19.

Workshop Relocation for 2019

The Twelfth Workshop on Fault-Tolerant Spaceborne Computing Employing New Technologies, 2019 will be associated with SMC-IT 2019

The Connected Enterprise Resiliency Conference continues in 2019 as Space Computing & Connected Enterprise Resilience Conference 2019

Workshop Relocation for 2018

The Eleventh Workshop on Fault-Tolerant Spaceborne Computing Employing New Technologies, 2018 was part of the Connected Enterprise Resiliency Conference 2018. We are working to put schedule online.

Previous Years

See for information on previous conferences.

Original file /spacecomputing.

Alternate source /ar/spacecomputing

Space Computing

Fault-Tolerant Spacebourne Computing Using New Technologies, 2017

The Tenth Workshop on
Fault-Tolerant Spaceborne Computing Employing New Technologies, 2017

CSRI Building
Sandia National Laboratories, Albuquerque, NM
May 30-June 2, 2017

Organized by: AFRL, Boeing, BAE, Honeywell, JPL, OGA, Sandia, USC/ISI

Click here for the schedule (or as a spreadsheet).
For reference, here are the links to the 20162015201420132012201120102009 and 2008 conference archives.


Jon Ballast, BoeingMarti Bancroft, Consultant
Richard Berger, BAELarry Bergman
Steve Crago, USC/ISIErik DeBenedictis, Sandia
Mitch FletcherKen Heffner, Honeywell
David Henriquez, JPLJesse Mee, AFRL
Hung Nguyen, SandiaJohn Samson
Rafi Some, JPL


This is notice of and a call for participation for the tenth workshop on space computing. The main sessions are May 31 and June 1, 2017, with additional working group sessions on May 30 and June 2, in Albuquerque. The afternoon session of June 1 will be closed (limited to invited partipants).

Like previous years, the topic will be R&D for next generation spacecraft computing systems, including hardware, security/trust, software, and applications.


This year, the meeting will be focused on multi-organizational projects and collaborative R&D that could contribute to building space processors and their applications. The organizers are issuing through this page an invitation for presentations on projects or capabilities. Please respond via e-mail to any of the organizers and include a semi-formal proposal.


We will have working groups as in past years. Some working groups have been organized already and we are soliciting ideas and participation in organizing others:

  • Cyber resilience
  • Architecture
  • Cubesats/smallsats
  • Machine learning/autonomy/Big Data
  • Memory technology

The conference has a capacity for other working groups, and we are soliciting ideas and organizers. If you would like to propose a working group, please contact one of the organizers.


The following will be held in conjunction with the meeting.

  • Opera/Maestro User Group


All attendees will require a DOE-issued badge when accessing Sandia’s facilities (but not the hotel). If you do not already have a DOE badge, attendees must contact Steven Garcia, (505) 284-5552 at least two weeks in advance and provide requested identifying information. Plan on picking up a badge at the Sandia badge office about 1/2 mile away before first entering DOE premises.


Foreign nationals will require a badge to access Sandia facilities but the process for foreign nationals is more time consuming than the process in the paragraph above. Foreign nationals should contact Steven Garcia, (505) 284-5552 immediately and should plan on stopping at the Sandia badge office about 1/2 mile away before first entering DOE premises.


Attendance is by invitation only. If you are in the industry and would like an invitation, please call Erik DeBenedictis (505) 284-4017 or e-mail The registration fee is $200. Register at the Sandia Webpay website at and selecting “Fault-Tolerant Spaceborne Computing using New Technologies 2017” as the event name.

If payment of a registration fee creates difficulties, please call Erik DeBenedictis (505) 284-4017 or e-mail and we will work out alternative arrangements.


The meeting will include information at various levels of sensitivity.

  • Some sessions on the schedule will indicate the information is sensitive (i. e. export controlled and proprietary). Attendees not eligible to receive specific information will be asked to leave the meeting room as needed.
  • There will be Government session that may be attended by only Government, FFRDC, and SETA employees.
  • While the entire meeting is by invitation only, there may be additional invitation-only sessions not posted on the Internet.


The associated hotel is the Albuquerque Marriott at 2101 Louisiana Blvd NE. Attendees can use this reservation link to make online reservations. Rate: $91 per night. The cut-off date for this rate is 5/15/2017.


The meeting will be held at several locations:

  • We expect all evening activities to be at the hotel.
  • Except as noted above, open portions of the meeting will be held at Sandia’s Computer Science Research Institute (CSRI) building on 1450 Innovation Parkway, Albuquerque, NM 87123 (map below). This facility is outside of Kirtland Air Force Base; visitors please do not try to enter Kirtland Air Force Base as you will probably not succeed and it will cause quite a delay. All attendees will need to make arrangements for a badge and then go to the badge office.
  • Closed portions of the meeting will be held in other buildings at Sandia; meet at the CSRI building for directions.


  • Erik DeBenedictis, Sandia,, (505) 284-4017
  • Jon Ballast, Boeing, jon.ballast at boeing dot com
  • Marti Bancroft, MBC, marti at dragonsden dot com
  • Richard Berger, Richard dot w dot berger at baesystems dot com
  • Larry Bergman, JPL, Larry dot A dot Bergman at jpl dot nasa dot gov
  • Steve Crago, USC/ISI, crago at isi dot edu
  • Mitch Fletcher, mitch dot fletcher at arrowheadse dot com
  • Ken Heffner, kenneth dot h dot heffner at honeywell dot com
  • David Henriquez, david dot a dot henriquez at jpl dot nasa dot gov
  • Jesse Mee, jesse dot mee at us dot af dot mil
  • Hung Nguyen, Sandia, hdnguye at sandia dot gov
  • John Samson, Honeywell, john dot r dot samson at honeywell dot com
  • Rafi Some, raphael dot r dot some at jpl dot nasa dot gov

Original files at

Alternate source /ar/spacecomputing/spc17.html