To illustrate the concept of FET-only adiabatic permutation stages as described in ref. 1, these test circuits demonstrate both 2LAL and SCRL 4-bit barrel shifters implemented with FET-only permutation stages.
The circuits are in a test harness comprising a four- or five-stage shift register preloaded with data patterns 1, 2, 4, 8 and a shift count pattern of 3, 3, 3, 3 places. The files should be available wherever the reader obtained this document, but the main files have been pasted into the appendix of this document as a failsafe. The circuits are designed for ngspice version 30 and use the built-in BSIM 3.3.0 transistor model, with voltage sources to alter gate bias (which is not realistic)
http://itrs.org/ar/CATC/barrel.pdf Alt. source /ar/CATC/barrel.pdf
http://itrs.org/ar/CATC/ZF003_1.0_Barrel.zip Alt. source /ar/CATC/ZF003_1.0_Barrel.zip