In this presentation we will provide an overview of both the Monarch chip and the Monarch Teraflop Processor. Next we will explore both the specific design choices made and obstacles that had to be overcome in applying it to DARPA's SAVi program. We will also examine some of the software design challenges that were easily met by Monarch's unique dataflow architecture. We will then look at some performance benchmarks for the system, as built. Next we will consider potential uses of the chip for space applications. We will conclude with a discussion of plans the next generation chip and compare it to other architectures.
Document date May 17, 2010.