The Seventh Meeting on...
Fault-Tolerant Spaceborne Computing Employing New Technologies, 2014

SCHEDULE

Location guide: All evening activities are at the hotel (hotel TBD), as noted. The main meeting place for the meeting is at the CSRI building near Sandia labs. The closed sessions will be elsewhere at Sandia, but meet at the CSRI building.

Monday
June 16		 Tuesday
June 17		 Wednesday
June 18		 Thursday
June 19
8:00 AM Background color legend:
Process
Government
Non-Government
Available
Closed session
Working Group
Working Group		 Breakfast and registration Breakfast Closed session
8:30 AM
9:00 AM Organizers, Meeting Process James Eagan, DARPA, software in space on distributed systems
9:15 AM ARFL Space Electronics Program (alternate topic possible), Gabe Mounce, ARFL Outbrief
9:30 AM Grzegorz Cieslewski, UFL and Sandia, Multibit Fault Injection for Field-Programmable Gate Arrays with Simple, Portable Fault Injector
10:00 AM Monte Goforth, NASA, NASA Avionic Architectures for Exploration (AAE) and Fault Tolerant Computing Ran Ginosar, Ramon Chips, Ltd., RC64: High Performance Rad-Hard Manycore (dial-in)
10:30 AM Break
10:45 AM Break
11:00 AM John Bellardo, Cal Poly SLO, CubeSats: Smaller Form-factor, Larger Flight Software
11:15 AM Sandra Faust Preference Appraisal Reinforcement Learning for Space Applications
11:30 AM Registration open at Sheraton Hotel (note that there is no meeting activity until 1 PM) Tyler Lovelly, UFL, Device Metrics and Benchmarking Analysis of Next-Generation Architectures for Space Computing
Noon Lunch (on your own) Lunch Lunch
1:00 PM Working groups (at hotel)
1. Fault tolerance
2. 3D		 Matthew French, ISI, Radiation Hardening by Software Techniques for COTS System on a Chip FPGAs Tony Sims, Aeroflex, LEON Expandable Application Platform (LEAP) evaluation
1:30 PM Cliff Kimmery, Honeywell, Next Generation Space Interconnect Standard (NGSIS) Warren Snapp, Boeing, 32nm Radiation Hardening By Design
2:00 PM Jon Ballast, Boeing, Boeing work on ARM-based processor Ian Troxel, Betrokor, Achieving High-Speed Box-to-Box Interconnects in Space Systems
2:30 PM Dale Rickard, BAE, Standards Based On-Board Processing for Fault Tolerant, High Performance Systems Grant Martin, Mathworks, Modeling Heterogeneous Architectures for Space Mission performance using Model-Based Design Techniques
3:00 PM Break Break Break
3:30 PM Working groups (at hotel)
(continued)		 Ken O'Neill, Microsemi, Fault Tolerant Computing for Space Applications with Microsemi FPGAs Paul Rutt, SEAKR, Iridium NEXT Reconfigurable Fault Tolerant Communication Processor (unconfirmed)
4:00 PM Brent Nelson, CHREC, BYU, Exploiting COTS for Space-Based Computing — Lessons Learned in CHREC Mel Butler, ARM, New developments in ARM architecture
4:30 PM Dan Elftman, Xilinx, Title TBD Outbrief on 3D and panel (1 hr)
5:00 PM Free Free Free
5:15 PM Reception (at hotel)
5:30 PM
6:00 PM Meet in dinner area
6:30 PM Working group (at hotel)
5. Maestro
7:00 PM Working groups (at hotel)
3. Software
4. Applications		 Dinner serving time
7:45 PM Hank Garrett, JPL, dinner talk There and Back Again: A Layman's Guide to Ultra-Reliability for Interstellar Missions.
10:00 PM End of Evening

Fault Tolerance Working Group

POC: Mitch Fletcher, Honeywell

Fault tolerance has been a topic of this conference from its inception. The general goal of the Fault Tolerant Working Group will be to assess the current status of fault tolerance computing. The working group will review the categories of fault tolerance (both hardware and software) necessary to implement future emerging mission needs. Additionally, there are a wide variety of new and emergency hardware and software techniques to implement fault tolerance. The working group will focus on how these emerging technologies align to the mission goals that require fault tolerance. There will be a continued focus on multi-core capability and the ability for additional hardware and software to leverage this capability. It is intended to have discussion about abstraction layers and how that supports (or doesn't support) implementation of fault tolerance. A small amount of time will be spent establishing potential cost risks associated with fault tolerant architecture implementations.

Brief talks are planned to stimulate interactive discussion.

3D Stacking Group

POC: Rafi Some, JPL

This working group will focus on 2.5D and 3D stacking technologies and their applications in space computing. Topics include: the state of the art in stacking technologies, processes, materials and characteristics, design tools, manufacturing options, testability, space qualification issues, standardization requirements and options, and architectural considerations for stack based high performance computing. The desired workshop output is a technology roadmap and identification of areas requiring research and development.

Applications Working Group

POC: Rafi Some, JPL and Erik DeBenedictis, Sandia

This working group will focus on applications for high performance computing in space. This unclassified session will address NASA, DOD, and other government and civilian applications that can be discussed in an unsecured facility. For those wTopics include: specific applications, computing models and paradigms for these applications, state of the art in tools and processes for code development and V&V. The desired working group output is a technology roadmap and identification of areas requiring research and development.

Maestro User Group

POC: Steve Crago, ISI and Marti Bancroft

The Maestro Users Group will be an open forum for current and potential users of the rad-hard Maestro many-core processor for space. The Maestro processor is based on the commercial Tile64 processor, has 49 cores, and provides up to 25 GFLOPS and 50 GOPS. The MTUG meeting will be an informal and interactive meeting of developers and users to discuss the current state of Maestro hardware and software technology, applications, performance, flight prospects, systems, and user experiences.

Document date June 20, 2014.