RC64 is a rad-hard shared memory many-core employing a hardware scheduler. It is designed for high performance, low power, and extensive I/O capabilities. The rad-hard 64-DSP-cores signal processor RC64 targets 35 GIPS, 140 GOPS and 35 single precision GFLOPS while dissipating less than 7 Watts, when packaged in a Class-S CCGA, and higher performance (and power) with Class-Y flip-chip assembly. RC64 supports DDR3 and SLC Flash memories and twelve 2.5/5.0 Gbps full duplex high speed SpaceFibre serial links. The programming model employs sequential fine-grain tasks and a separate task map to define task dependencies. RC64 will be implemented on a 65nm CMOS technology and qualified to ESCC9000. RC64 enables massive computing in arrays combining tens of chips, for future high performance telecommunication, SAR, navigation and earth observation satellites. A miniature multichip module combining RC64 with wideband rad-hard ADC and DAC is planned for enabling very large phased antenna arrays spread outside satellite bodies in high radiation environments for future telecommunications, SAR and navigation satellites. Several European FP7 R&D projects already support RC64 developments at multiple space organizations.