CHREC is a research consortium combining the efforts of four universities and more than 30 companies and government labs under the umbrella of the NSF Industry/University Cooperative Research Centers program. Space-based computing and reliability, especially in the context of FPGAs and other COTS technologies, has been a focus of the center since its beginnings. Our vision is to develop and validate techniques for creating hybrid architectures consisting of both reconfigurable hardware and multi-core processing platforms. In addition, we aim to develop architectures which appropriately mix COTS with rad hard devices to create high-performance computing platforms suitable for space. This talk will describe our previous COTS for space computing work in the areas of general mitigation techniques for FPGAs (TMR and scrubbing) and mitigation approaches for special-purpose units such as memories, soft-core processors, MGTs, etc. We will also present our ongoing work on verification including fault injection, radiation testing, and satellite deployment. Finally, we will describe CSP, a hybrid COTS/rad hard space processing platform being developed within CHREC.

Document date June 15, 2014.