COTS SRAM-based FPGAs have been able to meet many space environment mission requirements by adopting programming techniques such as bitstream scrubbing, modular redundancy of user logic, and error correction coding of user memories. These techniques have addressed classical ‘sea of gates’ FPGA architectures, while commercial industry has continued to innovate the FPGA architecture by integrating more dedicated IP, moving FPGAs into the System on a Chip architecture era. New IP types include embedded PowerPCs, Memory Management Units, Ethernet MAC cores, and high speed I/O, all of which require new radiation mitigation schemes. In this work, we focus on developing mitigation techniques for the embedded PowerPC 405 within the Xilinx Virtex4FX series, as it is the linchpin to enabling SoC FPGA designs. We present a scheme of radiation mitigation by software techniques focused on yielding high performance (<5% overhead) and mitigating all control flow errors. The scheme was tested utilizing a newly developed software fault emulator and laser testing. Results show processor hangs are eliminated, 100% of control errors are mitigated, and mean time between data corruption is increased by over 2.2x.

Document date June 6, 2014.