The Sixth Meeting on...
Fault-Tolerant Spaceborne Computing Employing New Technologies, 2013

SCHEDULE

		Tuesday May 28		Wednesday May 29		Thursday May 30
8:00 AM		Background color legend: Process Government Non-Government Available Working Group Working Group		Breakfast and registration		Breakfast
8:30 AM
9:00 AM				Organizers, Meeting Process		Rich Doyle, JPL, Space processor roadmap, strategy, and business issues
9:15 AM				Calvin Roman, ARFL, Space Systems Cyber Resilience discussion
10:00 AM				Warren Snapp, Boeing, RHBD II		Mitch Fletcher, Honeywell Perspectives of Orion and Future Vehicle Fault Tolerance, Honeywell
10:30 AM				Break		Break
11:00 AM				Steve Crago/Charles Neathery/JC Walters, ISI, Maestro		Darrel Raines, NASA, Fault Management design on the Orion Multi-Purpose Crew Vehicle (MPCV)
11:30 AM		Registration open at Sandia CSRI (note that there is no meeting activity until 1 PM)		Hans Zima, JPL, Towards a Unifying Software Framework for Power-Efficient Fault Tolerant Computing		Paul Murray, Dave Jungkind, SEAKR, Iridium processor overview
Noon		Lunch (on your own)		Lunch		Lunch
1:00 PM		Opera/Maestro User Group, Introduction		Mitch Fletcher, Honeywell, DM Cubesat		Mel Butler, ARM, Arm, the architecture for the digital world
1:15 PM		Hardware Status -- MDB capabilities and challenges
1:30 PM				Ken Mighel, NOAO, A User's Experience with Adding Fault Tolerance using Dependable Multiprocessor (DM) Middleware		Transport to closed session
1:45 PM		Software status -- MDE capabilities, challenges, and support
2:00 PM				David Hughart, Sandia, Total Ionizing Dose and Displacement Damage Effects on TaOx Memristive Memories		Closed session Agenda distributed via alternate e-mail Must stay on schedule for first speaker dial-in at 2:15
2:15 PM		Applications and benchmarks
2:30 PM				Gerry Taylor, Lockheed, NRAM Overview
3:00 PM		Break		Break
3:30 PM		User experiences and feedback		Beyond CMOS session introduction, Matt Marinella
3:35 PM				Erik DeBenedictis, Sandia, Beyond CMOS and Space Computing
4:00 PM				Art Edwards, AFRL, Robinson Pino, ARL
4:30 PM		Software Working Group I (at Sandia CSRI): Dr. Jeremy Kepner, MIT Lincoln Laboratory, MIT CS & AI Laboratory, MIT Math Dept, HPC and HPEC Benchmarking		Hugh Barnaby, Arizona State University, Radiation Effects in Redox/Resistive RAMs (ReRAM)
5:00 PM		Transport to hotel		Dinner on your own
5:15 PM		Reception (Sheraton Menaul)
5:30 PM
7:00 PM		Software Working Group II (Sheraton Menaul) Mitch Fletcher, Marti Bancroft, Larry Bergman, Overview and Goals of Working Group		Fault Tolerance Working Group (Sheraton Menaul)
7:15 PM
7:30 PM		Todd Carpenter, Adventium Labs, Hypervisor implementation for AFRL
7:45 PM
8:00 PM		Other suppliers verbal updates (anticipated Honeywell, WindRiver)
8:15 PM
8:30 PM		Discussion of redundancy management, implementation of trust, interaction of hardware and software enforcement
8:45 PM
9:00 PM
9:15 PM
9:30 PM		Open discussion (Reminder: All discussion will hav ediscussion on affordability)
9:45 PM

Beyond CMOS and Space Computing

The semiconductor industry is entering a transistion period from technology based on CMOS to successors. There are plans and schedules for a transition to an intermediate device called a FINFET and a series of candidates for a longer-terms solutions called the "Beyond CMOS" device. Space computing could benefit from both increased density and energy efficiency, but the radiation performance of these devices has yet to be determined.

Next Generation Space Processor (NGSP) High Performance Spaceflight Computing (HPSC) Next Steps at NASA and AFRL

Spaceflight computing can be aptly viewed as a “technology multiplier” for space missions, in that advances provide broad improvements in flight functions and capabilities, and enable new flight capabilities and mission scenarios, increasing science and exploration return.

To sharpen understanding of the gap between the current state of the practice and the near- to mid-term needs of NASA missions, a multi-center NASA team conducted a High Performance Spaceflight Computing (HPSC) formulation study, funded by the NASA Space Technology Game Changing Development Program.

As NASA’s HPSC study proceeded, AFRL and NASA identified significant overlap in future requirements and common interest in future flight computing. An agency-level partnership emerged, which is manifesting through joint investment in a Next Generation Space Processor (NGSP).

Software Working Group

As previously discussed by this group, flight software spans a wide number of system components typically broken into operation and application. There are several types of operation ranging from simple schedulers to complex real time OS systems. The more complex OS usually include service layers, numerical libraries, and fault management. Examples of applications within spacecraft systems include C&DH, GN&C, Communications (including DTN), Displays, Power management, and Health Management. All of these roles depend upon the application of the processor. This year's group will look at the state of the more complex off the shelf OS systems, and examine the relationship between OS and processing application. Also discussed will be relationship on trust models and the relationship of fault tolerant implementation upon the effectiveness of the fault management. Finally, the group will examine the methods to relate applications (previously discussed above) to the OS under which they execute. This discussion will include discussion of single and multiple processor implementations. A final topic intertwined within the discussion will be affordability of these techniques.

A User's Experience with Adding Fault Tolerance using Dependable Multiprocessor (DM) Middleware

I will describe my experience of porting two existing scientific applications, CRBLASTER and QLWFPC2, to the New Millennium Program (NMP) Space Technology 8 (ST8) to the Dependable Multiprocessor (DM). I used the technology-independent fault tolerant DM middleware to add fault tolerance to these two applications. As an independent third party developer, my experience was used to fulfill Criteria #6 of the seven criteria that needed to be satisfied by the DM project as part of the Technology Readiness Level 6 Validation Effort.

Space Systems Cyber Resiliency

Towards a Unifying Software Framework for Power-Efficient Fault Tolerant Computing

In this talk we discuss the design of an introspection-based software framework built around an inference engine and an associated knowledge base. A generalization of the JPL-developed SHINE system for the support of fault tolerance supports the runtime optimization of quantifiable performance and power consumption. Information about application and system behavior gathered in the knowledge base provides feedback to the compiler and the application developer for use in future compile-execute cycles.

Document date May 30, 2013.