The Fifth Workshop on...
Fault-Tolerant Spaceborne Computing Employing New Technologies, 2012

SCHEDULE

Location guide: Tuesday's afternoon activities, all evening activities, and the dinner on Thursday are at the Sheraton Menaul as noted. The main meeting place for the conference is at the CSRI building near Sandia labs. The high-level sessions will be elsewhere at Sandia, but meet at the CSRI building.

Tuesday
May 29		 Wednesday
May 30		 Thursday
May 31		 Friday
June 1
8:00 Breakfast and registration Breakfast Breakfast
8:30 AM Lorraine Fesq, JPL, Reflections on NASA's 2012 Fault Management Workshop Technical working group meeting (Sandia CSRI) (Friday Morning Schedule)
F: Maestro/Tilera User Group
9:00 AM Organizers, Workshop Process Dennis Polla, IARPA, Trusted Integrated Chips program
9:15 AM Background color legend:
Process
Government
Non-Government
Available
Working Group		 Lew Cohn, Rad Hard Foundry (9:15-9:45)
9:30 AM Nathan DeBardeleben, LANL, Resiliance: exascale vs. space
9:45 AM Steve Crago, ISI and Warren Snapp, Boeing, Maestro hardware and software test results
10 AM Break Break
10:30 AM Break Phil Campbell and TBD, Sandia, Cyber Security Next Steps

 Maestro/Tilera User Group
11 AM Rad-Hard By Design 32nm DDR2 SDRAM, Jon Ballast, Boeing Mike Johnson, NASA, NASA plans (dialin)
11:30 AM Registration (Sheraton Menaul) Carbon Nanotube Electronics for Space Computing Applications, James Dunning, Lockheed-Martin
11:45 AM Lunch (11:45-12:45 to allow more time for afternoon schedule)
NoonLunch (on your own) Lunch (Conference over)
1 PM Technical working group meeting
(Tuesday afternoon schedule)
A: Memory (Sheraton Menaul)		 Innovations in Advanced Spaceborne Computing, Alan D. George, University of Florida Panel session: Meeting misison needs for the coming decade: The interaction between power, performance, reliability and security requirements. Panelists: Rich Doyle, performance; Jeff Black, reliability; (unconfirmed), security; (unconfirmed), power; Nathan DeBardeleben, resiliance; (unconfirmed), applications. Heather Quinn POC.
1:30 PM Brian Wie, Steve Gurtin (dialin), Initial SEE Testing of Maestro
2 PM Stress Testing the 49-core Maestro Processor, Kenneth Mighell, NRAO
2:30 PM Update on Dependable Multiprocessor CubeSat Technology Development, John Samson, Honeywell Break
3 PM Break Break Closed Session (contact organizer for details)
3:30 PM Technical working group meetings (continued) Lessons Learned: System on a Chip Prototype, Mitch Fletcher, Honeywell
4 PM Vision-Based Navigation Using the Maestro Multi-core Processor, Joe Kochocki, Draper Laboratory
4:30 PM Flexible Space Computing Architectures with the Joint Architecture Standard (JAS), Paul Graham, Los Alamos
5:00 PM Reception (Sheraton Menaul) C: Next Generation Space Interconnect Standard (NGSIS) (Charles Collier, POC, meet until 6:15 PM)  
5:00 PM Dinner on your own
6:00 PMSit down dinner and dinner speaker Small Satellites to Flight Validate Spaceborne Computing Technologies, Dr. Charles D. Norton, JPL
7:00 PM Technical working group meetings (Sheraton Menaul) (Tuesday night schedule)
B: Fault tolerance		 Technical working group meeting (Sheraton Menaul) (Wednesday night schedule)
D: Software

A. Memory

(First Day: Tue, May 28, 1-5pm, at Sheraton Menaul):

Advanced Memories

Working group chair: Matt Marinella

Tuesday, May 29, 2012
1:00 PM - 4:00 PM
Sheraton Albuquerque Uptown

There are many R&D projects across industry and academia whose purpose is to create storage and memory using novel devices. These memories seem likely to appear in the commercial marketplace in a few years. They are likely to be replacements for memory sticks and Solid State Disks (SSDs) at first, yet may be available as DRAM (memory) replacements later on. Irrespective of radiation hardness, these devices could be important to the Government sector in areas such as Exascale computing (which is one target constituency of this working group). However, some of the novel device approaches appear to be radiation hard and could be specifically useful for space computing (which is another target consitutency).

The working group will include speakers and discussion on (1) the materials and function of advanced memories and (2) specific issues in environmental stress.

Tuesday Afternoon Schedule

Tuesday Afternoon
May 29
1:00 PM Matt Marinella, session introduction
1:30 PM Rad-Hard By Design 32nm DDR2 SDRAM, Jon Ballast, Boeing (related talk in plenary session)
2 PM Carbon Nanotube Electronics for Space Computing Applications, James Dunning, Lockheed-Martin (related talk in plenary session)
2:30 PM Rohit S. Shenoy, IBM, MIEC-based access devices to enable SCM
3 PM Conductive Bridge Random Access Memory, Michael Kozicki, Adesto
3:30 PM TiO2 Memristor Radiation Testing, Erica Deionno, Aerospace
4 PM High Total-dose Proton Radiation Tolerance in HfO2-based ReRAM Devices, Xiaoli He, SUNY-Albany
4:30 PM Discussion

B. Fault Tolerance Group

(First Day: Tue, May 29, 7 pm, at Sheraton Menaul):

Fault Tolerant (System Level) Working Group

Working Group Chair: Larry Bergman (JPL)
Working Group Co-Chair: Marti Bancroft (MBC)

Tuesday, May 29, 2012
7:00 PM - 9:00 PM
Sheraton Albuquerque Uptown

The general goal of the Fault Tolerant Working Group will be to assess the current status of fault tolerance / management system technologies (both hardware and software) for space borne computing, future emerging mission needs / requirements, and specific problems and solutions that require further development for multicore space borne avionics. One area of emphasis this year will be to focus on new challenges as well as new innovative solutions for implementing fault tolerance capability on multicore processor architectures.

Three brief talks are planned to stimulate interactive discussion:

Tuesday Night Schedule

Tuesday Night
May 29
7 PM Overview and Goals of Working Group (Larry Bergman/JPL)
7:10 PM Multicore Fault Tolerance Systems and Software -- Real Time and Robustness Considerations (Kim Gostelow, JPL)
7:30 PM Exascale Resiliency Roadmaps - Space Perspectives (Nathan DeBardeleben, Heather Quinn/LANL)
8:00 PM RHBD 3 Update (Warren Snapp/Boeing)
8:30 PM Discussion: Discuss remaining unsolved challenge areas / problems that need still need to be addressed with further research. Is the fault management robust enough for these multicore processors to be used in GN&C situations, or more appropriate for special purpose onboard data processing?
9:00 PM or when discussion winds down - ADJOURN

Wednesday Working Groups

C. Next Generation Space Interconnect Standard

(Second Day: Wed, May 30, 5 pm, at Sandia):

Next Generation Space Interconnect Standard

Meeting chair: Charles Collier

Wednesday, May 29, 2012
5:00 PM - 6:15 PM
Sandia CSRI

The NGSIS is interested in advancing the capabilities of intra-satellite interconnects through the use of commercially available high speed protocols and highly interoperable hardware suites. The group comprises both government and industry with the expressed task of advancement through stakeholder consensus.
Wednesday Afternoon
May 30
5 PM Introduction by Charles Patrick Collier - What is the NGSIS?
5:15 PM Overview of Current NGSIS Requirements
5:45 PM Open Forum and discussion of interconnect issues and solutions
6:15 PM End

D. Software

(Second Day: Wed, May 30, 7 pm, at Sheraton Menaul):

Software Working Group

Working Group Chair: Marti Bancroft (MBC)
Working Group Co-Chair: Larry Bergman (JPL)

Wednesday, May 30, 2012
7:00 PM - 10:00 PM
Sheraton Albuquerque Uptown

One challenge facing the space computing committee is comparing the relative merits of different emerging space computing/processor architectures against a range of onboard applications that might be experienced in various flight mission systems. Therefore, for 2012, we would like to focus on space computing benchmarks and their associated metrics. For example, in terms of performance, a variety of application benchmark kernels might be adopted from the ground based HPC community, such as the UCB 13 Dwarfs, HPCS kernels, etc. Are there still other application kernels that are unique to the space community that should be additionally considered (e.g., driven by controls, navigation)? Other system benchmarks/metrics to be discussed in this session include power/energy, fault tolerance, testability, and real-time - to name a few. At the conclusion of the workshop, a goal is to develop a language and set of measurement methods that can be used to compare the merits of a variety of space computer architectures against what is most optimum for given mission requirements. The underlying hypothesis is that for every mission class, there is/are a class of processor(s) that best suits its needs. This Working Group will also examine the remaining gaps and what still needs to be refined/developed for the future. Possibly a set of space computing benchmark standards may emerge.

Brief talks are planned to stimulate interactive discussion:

Wednesday Night Schedule

Wednesday Night
May 29
7:00 PM Overview and Goals of Working Group (Marti Bancroft, Larry Bergman)
7:20 PM A retrospective of HPC performance benchmarks (Yutao He/JPL?)
7:50 PM What is unique about the space computing domain? Other metrics/benchmarks? (tbd)
8:10 PM Operating systems and commercial tools (Mike Deliman/Windriver)
8:30 PM Roundtable Discussion (Moderators: Marti Bancroft, Larry Bergman)
10:00 PM ADJOURN (or whenever discussion ends)

Thursday Daytime Trust Session

E. Trust

(Third Day: Thu, May 31, morning, at CSRI):

Constructive Approaches to Trust

Session chair: Erik DeBenedictis

Thursday, May 31, 2012
10:30 AM - 1:30 PM
CSRI

Advances in technology over recent decades have caused a near national crisis in cyber security and supply chain trust. While it is popular to discuss the seriousness of the problem, this interactive session will take the approach of discussing constructive paths towards a remedy.

Someday there may be a grand strategy that addresses cyber security and supply chain trust, but we will have to get to that grand strategy in a series of steps. This interactive session will have speakers presenting specific principles and techniques that would each address some aspects of the overall security problem. The interactive period will be used for discussion of how the techiques presented could be applied to current activities or become part of a larger strategy.

Thursday Morning Schedule

Thursday Morning
May 31
9:00 AM Dennis Polla, IARPA, Trusted Integrated Chips program
9:30 AM Nathan DeBardeleben, LANL, Resiliance: exascale vs. space
10:00 AM Break
10:30 PM Phil Campbell and Moses Schwartz, Sandia, Cyber Security Next Steps

Friday Working Groups

F. Maestro/Tilera User Group

(Fourth Day: Fri, June 1, 8:30 am-noon, at Sandia)

Lead by: Marti Bancroft/Steve Crago

The Maestro User's Group will be an opportunity to talk to Maestro hardware and software developers and other users. There will be presentations and time for discussion. Topics of discussion are expected to include:

  • Development hardware
  • Development software
  • Applications for Maestro
  • Performance analysis and optimization
  • User experiences
  • Maestro and Tilera programming APIs, tools, and techniques

Friday Morning Schedule

8:30 AMWorking Group
10:00 AMBreak
10:30 AMWorking Group
12:00 PMConference over
Document date May 28, 2012.