[The abstract below is for a working group paper; the talk in this timeslor will be a programmatic talk related to the following technical paper...]
Research to be presented covers the hardware design changes proposed to the ISA in a single core processor (RAD750 as first example) to enable hardware support for different classification levels with secure separation. Current approaches on single core processors rely on software partitioning OS kernels. The hardware modifications proposed allow for a potential higher level of NSA approval and ensure that no contamination can occur between tasks. Although changes to the RAD750 are the example, this work could extend to other processor cores including potentially the "soft cores" used in FPGAs. The proposed approach will be contrasted with the available software options including GreenHills Integrity 178b RTOS.
Document date May 5, 2011.