The future of high performance computing, even as it is energized by the momentum of commercial semiconductor advances in the near term, will be challenged by critical emerging barriers in device physics, fabrication processes, heat, failures, concurrency, cost, and complexity. Radical departure from today's conventional practices and paradigms will be essential to vault the approaching capability chasm threatening future progress as a consequence of the inevitable flat-lining of Moore's Law in the nanoscale regime.

If the promise of continued performance gain beyond a few tens of Petaflops is to eventually deliver Exaflops and more to the hands of science, technology, defense, and society as a whole, a deep understanding of these impending stalling factors must be acquired, innovative strategies identified, and new technology trajectories plotted. It is imperative that from these insights a new roadmap be established for long term research in fundamental physics, device fabrication, models of parallel computation and programming, parallel algorithms, system structures and architectures, and user environments.

To that end, experts across a wide array of interrelated disciplines are coming together to assemble a first-ever map of the final trade-off space and possible paths through it to secure a a healthy future for US innovation and capability in computing, perhaps to the extremes of Zettaflops scale, a million times that likely at the end of this decade. The Workshop on the Frontiers of Extreme Computing will undertake to expose and characterize these barriers and project possible solution paths, proposing research directions to be initiated to ultimately address them.