Transitioning Moore’s Law to the Next Generation

Supercomputers have revolutionized science and defense in the last several decades, but additional effort will be required to maintain the trend. Moore’s Law has driven computers to be ever faster and progressively more capable of simulating larger problems with more sophisticated physics, thereby solving problems of progressively more importance to society. There is growing alarm that the current trend of “Moore’s Law” is reaching its end. Applications specialists in several fields foresee requirements up to 1 Zettaflops (10 million times the speed of the currently-fastest supercomputer) to complete just their missions. These requirements not only exceed the growth rate of Moore’s Law, but also exceed the physical limits of computers based on the physics currently underlying their operation. This opens a “mission gap” between the peak performances of supercomputers based on current trends and the mission needs of applications. There are options for filling this gap by developing new supercomputers based on disruptive technologies, yet the community must commit to one or a few to have sufficient resources to develop a solution. Furthermore, new and important problems based on optimization, inverses, and data analysis will have fundamentally larger resource requirements than simulations, with these new problems driving even higher computing requirements.

An important new workshop is being organized to match the continuum of important supercomputing applications with over-the-horizon computing methods fostered by the approaching nanoscale devices and to determine the limits of practical computing imposed by the constraints of basic physics and technology. Although not asserting a particular target performance value, a roadmap for staging advances coordinated with likely technology progress will be developed that will traverse the end of the reign of transistorized microprocessors and cross in to the domain of post-transistor nanotech devices and reversible logic at the end of the next decade. But even beyond this, participants will consider the factors determining the ultimate capabilities and what technologies may enable them and the problems these supercomputers will solve.

Organization and Key Topics:

• Problems to Solve. Identify important problems that can be solved with supercomputing and their resource requirements. In some cases, scaling up today’s applications will enable solution to new and important problems. In other cases, new problems will require new applications. Characterize the resource needs of the applications in decadal levels (1, 10, 100 Petaflops, 1, 10, 100 Exaflops, etc…), being mindful of the basic capabilities offered by Moore’s Law and disruptive technologies in terms of FLOPS, memory, I/O, interconnect, and other relevant features.
• Baseline Technologies. Identify the physical limits of supercomputer classes in use today, such as clusters, MPPs, and other approaches, based on the principles of physics and available roadmaps.
• Disruptive Technologies. Identify other classes of computation that may succeed the baseline technologies based on:
  • New architectures, such as Field Programmable Gate Arrays (FPGA), Processor in Memory (PIM), the Vector architecture (reborn), and others.
  • New devices capable of computing, such as RSFQ, CNFET, RTD, SET, Y-junctions, Moltronics, Quantum Dots, spintronics, and other devices of which the participants may be aware.
  • New ways of using devices, such as adiabatic logic design or reversible logic.
• Programming Methods. Billions have been invested in code for supercomputers, which is predominately composed of Fortran or C/C++ code with MPI or OpenMP communications. Determine which disruptive technologies are incompatible with existing code or programming methods, thereby classifying application missions into those that can leverage the existing software investment and which cannot.
• Reconciliation and Planning. Determine the suitability of running each application at particular scale levels with particular computing technologies, providing a matrix matching the ability of each relevant technology to run an application.
  • Nanoscale Technology directions and alternatives
  • Advanced computer architecture and parallel execution models
  • Low power technology and Reversible logic
  • Peta/Exascale applications and algorithms
  • Scalable operating and runtime system software
  • System engineering
  • Programming models and languages
  • Reliability and fault tolerance
  • Measuring success: metrics and methods

Charter to Groups

To establish the first long-term roadmap for the future of high performance computing from the near-term range of Petaflops-scale through to the asymptotic realm of extreme computing beyond an Exaflops as determined by the capabilities and limitations of future enabling technologies in order to identify critical research directions for continued growth in sustained performance for future applications and to determine the ultimate bounds on real world problems.

Organizers propose four groups of about 20 participants each in two general groups as follows:

• Working Group 1: Applications Pull
  This group will attempt to model society’s process for committing to develop and use new computer technology. The groups will consider progressively more powerful and esoteric technology options. To understand society’s motivation for supporting technology research, the group will first characterize new problems that become soluble with an uptick in technology. Then, the challenges of developing the technology will be assessed with a specific emphasis on the challenges (hardware, software, science, experimentation) needed to practically solve the problems identified. Reconciling the technology development costs with benefit to society becomes a roadmap for selling the process.
• Working Group 2: End of ITRS
  The ITRS extends semiconductor CMOS and DRAM technologies to a few tens of nanometers with increasing uncertainty due to cost, fabrication process, and power concerns. Using these projections at the end of the predicted technology path, this working group will summarize the technology operational properties, determine likely performance characteristics of both conventional and custom architectures implemented at this technology design point, and consider one or more challenging applications of importance that will both require and benefit from this level of capability. Key technical issues and challenges will be identified to achieve this level of capability and required research directions will be specified.
• Working Group 3: Nano-scale and other Leap-frog Technologies
  Nano-scale technology of the future will permit the definition, design, and fabrication of logic devices at near atomic scale that will yield component densities unlikely to be exceeded due to quantum limitations. Alternative technologies like RSFQ logic exploit superconductivity to deliver unprecedented switching rates (100s of GHz) at low power. Such innovations in asymptotic technologies will achieve ultimate capabilities from physical devices still operating within the domain of Boolean logic. This group will determine the level of performance that may be achieved within this technology realm, the computational structures and architectures that may be required and employed to exploit it, and the applications that may be enabled by it.
• Working Group 4: Extreme Technologies and Methods
  This group will explore computers unconstrained by anything except the laws of physics. It is known that reversible logic and quantum computing create another performance tier while still being recognizable as computers. Of course, participants are free to speculate on more far-fetched technologies like neural nets and DNA computers. Since the groups will have already considered simpler technologies in the Monday and Tuesday sessions, this session could find important problems that can only be solved with these esoteric technologies.