The Path to Extreme Supercomputing

A workshop held on October 12, 2004 in Santa Fe, New Mexico. This Web page is a record of the event, including the presentations as PowerPoint and PDF files. The workshop was attended by about 30 people.


Applications scientists envision applications for supercomputers up to 1 Zettaflops (1021 FLOPS), yet there is little consensus on how to build them. Recent studies of computational science applications show a continuum of truly important applications requiring supercomputers from today's 40 Teraflops to 1 Zettaflops over a period of several decades. This represents a faster growth than the historical trend of supercomputer performance. Furthermore, this magnitude of supercomputer performance exceeds the limits set by the laws of physics for clusters and Massively Parallel Processors (MPPs). This workshop will describe the challenges and potential solutions in order to inform participants of the issues and provide a basis for interdisciplinary cooperation.

Computer performance has advanced exponentially over many decades, but the path has not been smooth (bipolar transistors yielded to CMOS, scalars yielded to vectors, which yielded to parallel processing, and so forth). The theme of the workshop is that today's supercomputer technology will reach maturity if viewed narrowly, but can be continue to grow if we embrace change. The workshop will include a speakers describing a series of limits and corresponding technological changes that overcome the limits. With these changes, the workshop will show a plausible series of steps that can continue exponential progress to the Zettaflops level for supercomputing applications.


9:00-9:10Introductory comments.

William J. Camp, Director, Computation, Computers, Information and Mathematics (CCIM) Center, Sandia National Laboratories

9:10-9:15Workshop Organization.

Erik DeBenedictis, Sandia National Laboratories (pdf ppt)

9:15-10:00Application session: Climate Modeling. The speaker will describe climate modeling as a representative high-end application, its value to society, and the degree to which greater computing power yields more complete results. The speaker will also make some projections about the nature of high-end machines (FLOPS vs. memory vs. communications, etc.) for their application. For reference, the speaker is a co-author of the climate modeling section of the SCaLeS report that gives requirements to 1 Zettaflops.

Speaker: Philip Jones, Project Leader of the Climate Ocean and Sea Ice Modeling (COSIM), Los Alamos National Laboratory (Los Alamos National Laboratory technical report LA-UR-04-7128 pdf ppt)

10:00-10:30Limits of Current Technologies. This talk will explore the limits of computer technology assuming only incremental changes. These include the Landauer limit and a closely related reliability limit, setting peak performance for an ASCI-sized supercomputer to the low Exaflops realm. In addition, current microprocessor architectures have power efficiencies in the range of 1%, creating a lower limit in the mid Petaflops realm. Sandia National Laboratories technical report SAND2004-0959 is somewhat dated but gives the general idea of the material in this session.

Speaker: Erik DeBenedictis, Sandia National Laboratories (pdf ppt)


11:00-11:45Advanced Architecture. The session will be about raising performance through advanced architectures, yet focused on advances in semiconductor technology as predicted through Moore's Law. This session should identify the upside potential and limits of advanced architectures, using the work of the presenter as an example but generalizing the results. Advanced architectures can reach to the low Exaflops level.

Speaker: Peter Kogge, Ted H. McCourtney Professor of Computer Science, University of Notre Dame (pdf ppt)

11:45-12:30Software. This session will discuss the tie in between programming styles and the performance of underlying architectures. Existing code written in C++/Fortran with MPI/OpenMP require hardware with specific features (i. e. a microprocessor) that by necessity consume power and limit overall performance. Other programming styles (or perhaps elaborate compilers) can restructure code to work with more scalable hardware, yet these technologies will require further development and may place impositions on programmers.

Speaker: Bill Gropp, Associate Division Director, Senior Computer Scientist, Mathematics and Computer, Science Division, Argonne National Laboratories (pdf ppt)


2:00-2:45Logic -- Adiabatic and Reversible. This session will discuss substantial changes in the way logic and computing are done that can break through the limits of today's computer logic families. This session will provide an overview of adiabatic logic, reversible logic, and software techniques such as Bennett's algorithm. This session will discuss implementing these techniques with conventional transistors, and the resulting limits. With these techniques, there is no known upper limit on computer performance but the timeframe is quite long for transistorized solutions.

Speaker: Michael Frank, Assistant Professor, Florida State University (pdf ppt)

2:45-3:30Post-Transistor Devices. The speaker will talk on new devices that can offer performance vastly exceeding the transistor, focusing on the Quantum Cellular Automata (QCA) or Quantum Dot. This presentation will describe the basic nature of a new device, its potential to drive a future supercomputer, and the challenges required to refine the technology to a practical and manufacturable state. Post-transistor devices show promise of reaching the Zettaflops level in a few decades if used in conjunction with other methods. For background information, see the Notre Dame QCA website.

Speaker: Craig Lent, Freimann Professor of Engineering, Department of Electrical Engineering University of Notre Dame Notre Dame (pdf ppt)


4:00-5:30Roadmap and Change. Panel: "How much should we change supercomputing to enable the applications that are important to us, and how fast."


  • Thomas Sterling, Faculty Associate, Center for Advanced Computing Research, Caltech/JPL (pdf ppt)
  • Horst D. Simon, Director, National Energy Research Scientific Computing (NERSC) Center and Director, Computational Research Division, Lawrence Berkeley National Laboratory (pdf ppt)
  • Dr. David P. Koester, The MITRE Corporation, representing DARPA High Productivity Computing Systems (HPCS) Productivity Team (pdf ppt)
  • Terry Michalske, Director, Center for Integrated Nanotechnologies (CINT), Sandia National Laboratories
  • Fred Johnson, Department of Energy, Office of Science
  • William J. Camp, Sandia National Laboratories

Contact Information

Erik P. DeBenedictis
Sandia National Laboratories
(505) 284-4017

Organizing Committee:
Erik P. DeBenedictis, Sandia National Laboratories
Peter Kogge, University of Notre Dame
Thomas Sterling, Caltech/JPL
Michael Frank, University of Florida

This page updated October 13, 2004