Prospects for Computing Beyond CMOS
Thomas N Theis, Director, Physical Sciences IBM Research, T.J. Watson Research Center
In the last few years, microprocessor clock speeds have ceased their historic rate of exponential advance. The root cause is the failure of traditional scaling rules for devices at the 90 nm generation and beyond, resulting in system designs that are severely constrained by economic limits on allowable power dissipation. While significant further improvements in CMOS FET technology are likely, I argue on physical grounds that dramatic advances in processor clock speeds will only be possible by moving to energy-conserving (also called "adiabatic" or "reversible") circuit designs. Careful studies in the mid-nineties showed that such circuits offer no advantage over conventional low-power circuits when built with CMOS transistors. Today, we see an explosion of interest in "post-CMOS" devices. I argue that a new device, much better suited to energy-conserving circuits than the FET, is physically possible, and I discuss the necessary attributes of such a device.